{"id":1026,"date":"2019-12-18T19:54:22","date_gmt":"2019-12-18T19:54:22","guid":{"rendered":"https:\/\/ibex.tech\/embedded\/?p=1026"},"modified":"2022-02-18T15:37:48","modified_gmt":"2022-02-18T15:37:48","slug":"pic32-memory","status":"publish","type":"post","link":"https:\/\/ibex.tech\/embedded\/microchip\/pic32\/xc32\/memory-registers\/pic32-memory","title":{"rendered":"PIC32 Memory"},"content":{"rendered":"\n<p>PIC32 memory sizes are specified in bytes, but it stores 32bit words.  Addressing is byte based, incrementing by 4 for each 32bit instruction.<\/p>\n\n\n\n<p>PIC32&#8217;s implement two address schemes: virtual and physical.<\/p>\n\n\n\n<p>All hardware resources (program memory, data memory and peripherals) are located at their respective physical addresses.<\/p>\n\n\n\n<p>Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals.<\/p>\n\n\n\n<p>Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.<\/p>\n\n\n\n<p>KSEG0 and KSEG1 both translate to the same physical memory. They are created as separate memory segments because KSEG0 can be cached by the application whilst KSEG1 cannot:<\/p>\n\n\n\n<p>KSEG0 is cacheable<\/p>\n\n\n\n<p>KSEG1 is not cacheable. On chip peripherals are only accessible through this segment (SFR not present in the KSEG0 memory range)<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Example &#8211; PIC32MX534F064H<\/h4>\n\n\n\n<p>Program memory:<br>    0x1D000000 &#8211; 0x1D00FFFF<br>    0x9D000000 &#8211; 0x9D00FFFF (virtual memory mapped)<br>    0xBD000000 &#8211; 0xBD00FFFF (virtual memory mapped)<\/p>\n\n\n\n<p>    0x1D000000 &#8211; 0x1D00FFFF = 65536 addresses = 64KB program memory as specified in datasheet.<\/p>\n\n\n\n<p>PIC32 memory is 32bit words, addressing is byte based and increments by 4 for each instruction, so:<br>    64KB of program memory = 16K x 32bit instructions<\/p>\n","protected":false},"excerpt":{"rendered":"<p>PIC32 memory sizes are specified in bytes, but it stores 32bit words. Addressing is byte based, incrementing by 4 for each 32bit instruction. PIC32&#8217;s implement two address schemes: virtual and physical. All hardware resources (program memory, data memory and peripherals) are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[84],"tags":[],"class_list":["post-1026","post","type-post","status-publish","format-standard","hentry","category-memory-registers"],"_links":{"self":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/1026","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/comments?post=1026"}],"version-history":[{"count":3,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/1026\/revisions"}],"predecessor-version":[{"id":1031,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/1026\/revisions\/1031"}],"wp:attachment":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/media?parent=1026"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/categories?post=1026"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/tags?post=1026"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}