\n \n<\/p>\n
\nPIC32 stores 32bit words with address incrementing by 4 for each instruction\n<\/p>\n
\nPIC32's implement two address schemes: virtual and physical.\n<\/p>\n
\nAll hardware resources (program memory, data memory and peripherals) are located at their respective physical addresses.\n<\/p>\n
\nVirtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals.\n<\/p>\n
\nPhysical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU.\n<\/p>\n
\nKSEG0 and KSEG1 both translate to the same physical memory. They are created as separate memory segments because KSEG0 can be cached by the application whilst KSEG1 cannot:\n<\/p>\n
\nKSEG0 is cacheable\n<\/p>\n
\nKSEG1 is not cacheable. On chip peripherals are only accessible through this segment (SFR not present in the KSEG0 memory range)\n<\/p>\n
\nThe following works for V2.00 and above of the C32 compiler\n<\/p>\n
\r\n\r\n#define FLASH_FIRMWARE_VALUES_LOCATION\t\t\t0x9D07FFF8\r\n\r\nconst BYTE firmware_prog_memory_values[] __attribute__((section("firmware_prog_memory_values"),address(FLASH_FIRMWARE_VALUES_LOCATION), space(prog))) =\r\n{\r\n\t0x12,\r\n\t0x34,\r\n\t0x56,\r\n\t0x78\r\n};\r\n<\/code><\/pre>\n\nReading the values in your code
\n<\/h5>\n\r\n\r\n\tp_flash = (DWORD*)FLASH_FIRMWARE_VALUES_LOCATION;\r\n\tdw_temp.Val = p_flash[0];\r\n\tmagic_marker.v[1] = dw_temp.v[0];\r\n\tmagic_marker.v[0] = dw_temp.v[1];\r\n<\/code><\/pre>\n\nC32 Storing in program memory example
\n<\/h4>\n
\nFrom USB Device – Mass Storage – Internal Flash Demo – XC32 – PIC32MX460F512L PIM.mcp\n<\/p>\n
\r\n\r\n\/\/.MDD_FILES doesn't need to have been defined in the linker script etc, its just a name to be applied to this\r\n\/\/space(prog) forces the allocation into program memory - newer version of the C32 compiler changed from stored const memory in program memory to ram for some unknown reason\r\n#define MY_ATTRIBUTES __attribute__ ((aligned (ERASE_BLOCK_SIZE),section(".MDD_FILES"),space(prog)))\r\n\r\nconst BYTE MY_ATTRIBUTES MasterBootRecord[MEDIA_SECTOR_SIZE] =\r\n{\r\n<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":" PIC32 stores 32bit words with address incrementing by 4 for each instruction PIC32's implement two address schemes: virtual and physical. All hardware resources (program memory, data memory and peripherals) are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[20],"tags":[],"class_list":["post-112","post","type-post","status-publish","format-standard","hentry","category-c32-compiler"],"_links":{"self":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/112","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/comments?post=112"}],"version-history":[{"count":6,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/112\/revisions"}],"predecessor-version":[{"id":548,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/112\/revisions\/548"}],"wp:attachment":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/media?parent=112"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/categories?post=112"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/tags?post=112"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}