{"id":253,"date":"2013-04-04T13:15:43","date_gmt":"2013-04-04T13:15:43","guid":{"rendered":"http:\/\/www.electronic-products-development.com\/?p=253"},"modified":"2022-02-18T15:37:49","modified_gmt":"2022-02-18T15:37:49","slug":"spi-pic24hj","status":"publish","type":"post","link":"https:\/\/ibex.tech\/embedded\/microchip\/pic24\/c30-compiler\/spi-pic24hj","title":{"rendered":"SPI"},"content":{"rendered":"<h4>\nSPI Master<br \/>\n<\/h4>\n<pre>\r\n<code>\r\n\t\/\/----- SETUP SPI 1 -----\r\n\t\/\/Used for: \r\n\tw_temp = SPI1BUF;\r\n\tSPI1STAT = 0;\r\n\tSPI1CON1 = 0b0000001100100001;\t\/\/SPI in master mode (SPI1STATbits.SPIEN must be 0 to write to this register)\r\n\t\t\t\t\t\t\t\t\t\/\/Data is valid on the rising edge of the clock (Transmit occurs on transition from active to idle clock state)\r\n\t\t\t\t\t\t\t\t\t\/\/Clock low in idle bus state\r\n\tSPI1CON1bits.PPRE1 = 1;\t\t\t\/\/Prescallers 4:1 1:1 = 10MHz (max possible from this device)\r\n\tSPI1CON1bits.PPRE0 = 0;\r\n\tSPI1CON1bits.SPRE2 = 1;\r\n\tSPI1CON1bits.SPRE1 = 1;\r\n\tSPI1CON1bits.SPRE0 = 1;\r\n\tSPI1CON2 = 0;\r\n\tSPI1STATbits.SPIEN = 1;\t\t\t\/\/Enable the port\r\n<\/code><\/pre>\n<p>\n&nbsp;\n<\/p>\n<h4>\nSPI Slave<br \/>\n<\/h4>\n<h5>\nInitialise<br \/>\n<\/h5>\n<pre>\r\n<code>\r\n\t\/\/----- SETUP SPI 2 -----\r\n\t\/\/Used for: \r\n\tSPI2BUF = 0;\r\n\tIFS2bits.SPI2IF = 0;\t\t\t\/\/Clear the Interrupt Flag\r\n\tIEC2bits.SPI2IE = 0;\t\t\t\/\/Disable The Interrupt\r\n\r\n\tSPI2CON1bits.DISSCK = 0;\t\t\/\/Internal Serial Clock is Enabled\r\n\tSPI2CON1bits.DISSDO = 0;\t\t\/\/SDOx pin is controlled by the module\r\n\tSPI2CON1bits.MODE16 = 0;\t\t\/\/Communication is byte-wide (8 bits)\r\n\tSPI2CON1bits.SMP = 0;\t\t\t\/\/Input Data is sampled at the middle of data Output time\r\n\tSPI2CON1bits.CKE = 1;\t\t\t\/\/Data is valid on the rising edge of the clock (Transmit occurs on transition from active to idle clock state)\r\n\tSPI2CON1bits.CKP = 0;\t\t\t\/\/Clock low in idle bus state\r\n\tSPI2CON1bits.MSTEN = 0;\t\t\t\/\/Master Mode disabled\r\n\tSPI2CON1bits.SSEN = 1;\t\t\t\/\/SS pin enabled (the SSx pin must be enabled in Slave mode when CKE = 1)\r\n\tSPI2STATbits.SPIROV =0;\t\t\t\/\/No Receive Overflow has Occurred\r\n\tSPI2STATbits.SPIEN = 1;\t\t\t\/\/Enable SPI Module\r\n\t\r\n\tIFS2bits.SPI2IF = 0;\t\t\t\/\/Clear the Interrupt Flag\r\n\tIEC2bits.SPI2IE = 1;\t\t\t\/\/Enable The Interrupt\r\n<\/code><\/pre>\n<h5>\nInterrupt<br \/>\n<\/h5>\n<pre>\r\n<code>\r\n\r\n\/\/***************************************\r\n\/\/***************************************\r\n\/\/********** SPI2 RX INTERRUPT **********\r\n\/\/***************************************\r\n\/\/***************************************\r\nvoid __attribute__((__interrupt__,__auto_psv__)) _SPI2Interrupt(void)\r\n{\r\n\tWORD data;\r\n\r\n\tif (SPI2STATbits.SPIROV)\r\n\t{\r\n\t\t\/\/----- OVERFLOW ERROR -----\r\n\t\t\/\/If a new data word has been shifted into SPIxSR and the previous SPIxBUF contents have not been read, the SPIROV bit (SPIxSTAT&lt;6&gt;) is set.\r\n\t\t\/\/Any received data in SPIxSR is not transferred, and further data reception is disabled until the SPIROV bit is cleared. The SPIROV bit is not\r\n\t\t\/\/cleared automatically by the module; it must be cleared by the user application.\r\n\t\tdata = SPI2BUF;\r\n\t\tSPI2STATbits.SPIROV = 0;\r\n\t\tIFS2bits.SPI2IF = 0;\t\t\t\/\/Clear the Interrupt Flag\r\n\t\treturn;\r\n\t}\r\n\r\n\t\/\/----- READ THE DATA -----\r\n\tdata = SPI2BUF;\r\n\r\n\t\/\/----- WRITE THE NEXT DATA BYTE -----\r\n\t\/\/This needs to happen befoer the next byte\/word is received.  This irq is triggered 1\/2 bit time before the end of the last bit of this byte\/word, so if the master is fast we must service to her before the start of the first bit of the next byte\/word.\r\n\tSPI2BUF = data + 1;\t\t\t\/\/Send back what we received + 1\r\n\t\r\n\tIFS2bits.SPI2IF = 0;\t\t\t\/\/Clear the Interrupt Flag\r\n}\r\n\r\n\/\/******************************************\r\n\/\/******************************************\r\n\/\/********** SPI2 ERROR INTERRUPT **********\r\n\/\/******************************************\r\n\/\/******************************************\r\n\/\/SPIx Error Interrupt Flag (SPIxEIF) is set when the SPIROV bit is set. This interrupt flag must be cleared in software. The actual SPIx Error Interrupt\r\n\/\/is generated only when the corresponding SPIxEIE bit is set in the IECn Control register.\r\n\/*\r\nvoid __attribute__((__interrupt__,__auto_psv__)) _SPI2ErrInterrupt(void)\r\n{\r\n\t\r\n}\r\n*\/\r\n<\/code><\/pre>\n<p>\n&nbsp;\n<\/p>\n<p>\n&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>SPI Master \/\/&#8212;&#8211; SETUP SPI 1 &#8212;&#8211; \/\/Used for: w_temp = SPI1BUF; SPI1STAT = 0; SPI1CON1 = 0b0000001100100001; \/\/SPI in master mode (SPI1STATbits.SPIEN must be 0 to write to this register) \/\/Data is valid on the rising edge of the clock (Transmit occurs on transition from active to idle clock state) \/\/Clock low in idle [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[17],"tags":[],"class_list":["post-253","post","type-post","status-publish","format-standard","hentry","category-c30-compiler"],"_links":{"self":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/253","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/comments?post=253"}],"version-history":[{"count":10,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/253\/revisions"}],"predecessor-version":[{"id":460,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/253\/revisions\/460"}],"wp:attachment":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/media?parent=253"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/categories?post=253"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/tags?post=253"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}