{"id":502,"date":"2014-09-05T14:59:14","date_gmt":"2014-09-05T14:59:14","guid":{"rendered":"https:\/\/ibex.tech\/embedded\/?p=502"},"modified":"2022-02-18T15:37:49","modified_gmt":"2022-02-18T15:37:49","slug":"using-assembly-code","status":"publish","type":"post","link":"https:\/\/ibex.tech\/embedded\/microchip\/pic18\/xc8-compiler\/converting-from-c18-projects-to-xc8\/using-assembly-code","title":{"rendered":"Using assembly code"},"content":{"rendered":"<p>\n&nbsp;\n<\/p>\n<h4>\nSimple example of changes to typical heartbeat timer irq inline assembly<br \/>\n<\/h4>\n<h5>\nOriginal&nbsp;C18 Code<br \/>\n<\/h5>\n<pre>\r\n<code>\r\n\t_asm\r\n\t\/\/Reset timer for next rollover\r\n\tmovff\tTMR0L,uc_asm_irq_temp\t\t\t\/\/read_current_timer_value (read low byte loads high byte)\r\n\tmovff\tTMR0H,uc_asm_irq_temp1\r\n\tmovlw\t0xbb\r\n\taddwf\tuc_asm_irq_temp,1,0\t\t\t\t\/\/(1 = file register, 0 = access ram)\r\n\tmovlw\t0x3c\r\n\taddwfc\tuc_asm_irq_temp1,1,0\t\t\t\/\/(1 = file register, 0 = access ram)\r\n\tmovff\tuc_asm_irq_temp1,TMR0H\t\t\t\/\/Store new value (high byte first)\r\n\tmovff\tuc_asm_irq_temp,TMR0L\r\n\t_endasm\r\n<\/code><\/pre>\n<h5>\nNewer XC Code<br \/>\n<\/h5>\n<p>\nIMPORTANT &#8211; MAKE SURE XC8 OPTIMIZATIONS &#39;ADDRESS QUALIFIERS&#39; IS SET TO &#39;REQUIRE&#39;&nbsp;\n<\/p>\n<pre>\r\n<code>\r\n\t#asm\r\n\tGLOBAL _uc_asm_irq_temp\r\n\tGLOBAL _uc_asm_irq_temp1\r\n\t\/\/Reset timer for next rollover\r\n\tmovff\tTMR0L,_uc_asm_irq_temp\t\t\t\/\/read_current_timer_value (read low byte loads high byte)\r\n\tmovff\tTMR0H,_uc_asm_irq_temp1\r\n\tmovlw\t0xfb\r\n\taddwf\t_uc_asm_irq_temp,f,c\t\t\t\t\/\/(f = file register, c = common\/access ram)\r\n\tmovlw\t0xd8\r\n\taddwfc\t_uc_asm_irq_temp1,f,c\t\t\t\/\/(f = file register, c = common\/access ram)\r\n\tmovff\t_uc_asm_irq_temp1,TMR0H\t\t\t\/\/Store new value (high byte first)\r\n\tmovff\t_uc_asm_irq_temp,TMR0L\r\n\t#endasm\r\n<\/code><\/pre>\n<p>\nWhat changed:\n<\/p>\n<p style=\"margin-left: 40px;\">\n_asm and _endasm change to #asm and #endasm<br \/>\nVariables are declared in C without a leading underscore, but to be used in assembler code they must have a leading underscore added and be declared using GLOBAL.\n<\/p>\n<h5>\nPrevious XC Code<br \/>\n<\/h5>\n<p>\nNewer versions of XC8 generate a &quot;error: (876) syntax error&quot; to the use of the below. It turns out &quot;,1,0&quot; on the end of the addwf and addwfc lines are the issue (even though these numeric values are specified for use in device datasheets). &nbsp;\n<\/p>\n<p style=\"margin-left: 40px;\">\nThe &#39;1&#39; needs to change to &#39;f&#39; for file register.\n<\/p>\n<p style=\"margin-left: 40px;\">\nThe &#39;0&#39; needs to change to &#39;c&#39; for common memory \/ access ram (the alternative would be &#39;b&#39; for bank select register).\n<\/p>\n<p>\n<em>IMPORTANT &#8211; MAKE SURE XC8 OPTIMIZATIONS &#39;ADDRESS QUALIFIERS&#39; IS SET TO &#39;REQUIRE&#39;&nbsp;<\/em>\n<\/p>\n<pre>\r\n<code>\r\n\t#asm\r\n\tGLOBAL _uc_asm_irq_temp\r\n\tGLOBAL _uc_asm_irq_temp1\r\n\t\/\/Reset timer for next rollover\r\n\tmovff\tTMR0L,_uc_asm_irq_temp\t\t\t\/\/read_current_timer_value (read low byte loads high byte)\r\n\tmovff\tTMR0H,_uc_asm_irq_temp1\r\n\tmovlw\t0xbb\r\n\taddwf\t_uc_asm_irq_temp,1,0\t\t\t\t\/\/(1 = file register, 0 = access ram)\r\n\tmovlw\t0x3c\r\n\taddwfc\t_uc_asm_irq_temp1,1,0\t\t\t\/\/(1 = file register, 0 = access ram)\r\n\tmovff\t_uc_asm_irq_temp1,TMR0H\t\t\t\/\/Store new value (high byte first)\r\n\tmovff\t_uc_asm_irq_temp,TMR0L\r\n\t#endasm\r\n<\/code><\/pre>\n<p>\n&nbsp;\n<\/p>\n<p>\nFor more information see the&nbsp;&quot;C18 to XC8 C Compiler Migration Guide&quot; as there are some key differences\n<\/p>\n<h4>\nInstruction Arguments<br \/>\n<\/h4>\n<p>\nDestination select bit\n<\/p>\n<p style=\"margin-left: 40px;\">\nw = store result in WREG (0)<br \/>\nf = store result in file register f (1)\n<\/p>\n<p>\nRAM access bit\n<\/p>\n<p style=\"margin-left: 40px;\">\nc = common \/ access ram (0)<br \/>\nb =&nbsp;bank select register (1)\n<\/p>\n<p>\n&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>&nbsp; Simple example of changes to typical heartbeat timer irq inline assembly Original&nbsp;C18 Code _asm \/\/Reset timer for next rollover movff TMR0L,uc_asm_irq_temp \/\/read_current_timer_value (read low byte loads high byte) movff TMR0H,uc_asm_irq_temp1 movlw 0xbb addwf uc_asm_irq_temp,1,0 \/\/(1 = file register, 0 = access ram) movlw 0x3c addwfc uc_asm_irq_temp1,1,0 \/\/(1 = file register, 0 = access ram) [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[55,56],"tags":[],"class_list":["post-502","post","type-post","status-publish","format-standard","hentry","category-converting-from-c18-projects-to-xc8","category-basic-template-project-changes"],"_links":{"self":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/502","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/comments?post=502"}],"version-history":[{"count":7,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/502\/revisions"}],"predecessor-version":[{"id":602,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/posts\/502\/revisions\/602"}],"wp:attachment":[{"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/media?parent=502"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/categories?post=502"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ibex.tech\/embedded\/wp-json\/wp\/v2\/tags?post=502"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}